This disclosure relates to microfabrication including microfabrication of integrated circuits.
Semiconductor manufacturing includes photolithographic and patterning processes. Some photolithographic processes include coating a wafer with a thin film of bottom anti-reflective coating (BARC) material, followed by coating with a resist, and then exposing the wafer to a pattern of light as one of many process steps for creating microchips. Photolithographic and patterning processes typically benefit from a planar surface for depositing the various films and resists used to pattern and expose a wafer. Films can be specified to have a particular height and be planarized to within certain dimensions, depending on a given fabrication process.
Planarization is commonly performed using a process known as Chemical Mechanical Polishing (CMP). CMP is a process that uses corrosive chemicals and a polishing pad to planarize the surface of a wafer, similar to how wet sanding works. CMP can planarize insulators and conductors in multilevel structures. This planarization is used to stack more electronics onto another layer of a wafer, or to planarize the wafer for photo lithographic patterning. CMP is also used to fine tune the lithographic exposure process by setting a resist to a known height to optimize the exposure surface.